1. Field of the Invention
The present invention relates to a method of fabricating lightly doped drains (LDDs) of different resistance values, and more particularly, to a method that is applied to SRAM for increasing a cell ratio of the SRAM.
2. Description of the Prior Art
In a semiconductor wafer, memory cells are divided into dynamic random access memory (DRAM) and static random access memory (SRAM) by a way of data storage. DRAM uses an electrically charged state of a capacitor in the memory cell to determine stored logical data, and SRAM uses conductive states of transistors in the memory cell to determine stored logical data. Compared to DRAM, SRAM has advantages of high speed, low power consumption, simple operation, easy design and not needing regular refresh. However, because six transistors are required for each SRAM memory cell, SRAM integration is hard to improve.
Please refer to FIG. 1, which is a circuit diagram of an SRAM cell 10 in full CMOS. The traditional SRAM cell 10 has two PMOS-type load transistors 12, 14 functioning as a load element, two NMOS-type driver transistors 16, 18 functioning as a driver, and two NMOS-type access transistors 20, 22 for data access in the SRAM.
As shown in FIG. 1, sources of the load transistors 12, 14 are connected to VDD, and drains of the load transistors 12, 14 are connected in series to drains of the driver transistors 16, 18 at nodes 24, 26, respectively. Sources of the driver transistors 16, 18 are electrically connected to VSS. In addition, gates of the load transistors 12, 14 are connected to gates of the driver transistors 16, 18. These connection lines are cross-coupled with nodes 26, 24, respectively. Both gates of the access transistors 20, 22 are connected to a word line 27. Sources of the access transistors 20, 22 are connected to a bit line 28 and a bit line 29, respectively, and drains of the access transistors 20, 22 are connected to drains of the driver transistors 16, 18 at nodes 24, 26, respectively.
Taking logic xe2x80x9c1xe2x80x9d storage as an example, when storing data, the access transistors 20, 22 are turned on by adjusting a voltage of the word line 27, in order to store data at nodes 24, 26. A higher voltage state (3V) is inputted to the bit line 28 and a lower voltage state (0V) is inputted to the bit line 29. Therefore, the load transistor 12 and the driver transistor 18 are turned on, and the load transistor 14 and the driver transistor 16 are turned off. Therefore, a portion of the current flow in node 26 runs to VSS via the turned on driver transistor 18, but the current flow in the node 24 cannot run to the VSS via the turned off driver transistor 16. Consequently, node 24 is in a xe2x80x9chigherxe2x80x9d voltage state and node 26 is in a xe2x80x9clowerxe2x80x9d voltage state. Finally, the word line 27 is turned off, so that nodes 24, 26 are locked to maintain the same state, and the data are stored at the nodes 24, 26, respectively.
However, the data storage may be damaged by noise and an unbalanced threshold, and the data storage ability is related to cell ratio. Cell ratio is a driver transistor to access transistor current driving capability ratio. As shown in FIG. 1, in a case where the data is stored with a xe2x80x9clowerxe2x80x9d state at node 24 and a xe2x80x9chigherxe2x80x9d state at node 26, the voltage of node 24 is determined by the current flow magnitude of the driver transistor 16, 18 to the access transistors 20, 22. If the current flow passing the driver transistors 16, 18 is increased and current flow passing the access transistors 20, 22 is decreased, that is increasing cell ratio, the node 24 is intended to maintain the xe2x80x9clowerxe2x80x9d state. Even during a process of reading the cell memory data, the voltage of the node 24 is not drastically changed from the xe2x80x9clowerxe2x80x9d state when the voltages of bit lines 28, 29 are changed to turn on the access transistors 20, 22. Because the voltage of node 24 is not changed heavily, the cross-coupled node 26 is still maintained in the xe2x80x9chigherxe2x80x9d state and the data storage state is not changed.
Therefore, in order to improve performance and stability, the cell ratio of SRAM must be larger than 1. Traditional approaches to increase cell ratio are:
1. Increasing channel width or channel length.
The approach is increasing channel width of the driver transistor or increasing channel length of the access transistor to adjust the current flowing through the driver transistor and access transistor. Although the approach can directly increase cell ratio, increasing the channel width and channel length leads to SRAM size increase, thereby seriously affecting the integration of the SRAM process.
2. Using different threshold voltages or thicknesses of gate oxides.
The approach uses two different masks to form different thicknesses of gate oxides during a fabrication process of the driver transistor and the access transistor, thereby leading to different gate threshold voltages of these two transistors, so as to affect the ratio of currents. However, the approach needs additional mask processes and incurs a higher fabrication cost.
It is therefore a primary objective of the present invention to provide a fabrication method for increasing SRAM cell ratio, and solving the above-mentioned problems.
It is a secondary objective of the present invention to provide a method of forming LDDs having different resistance values, so as to increase a cell ratio in the SRAM.
In accordance with the claim invention, the method first involves providing a semiconductor wafer, the semiconductor wafer comprising a first active area and a second active area set on the substrate. Secondly, a first gate and a second gate are formed on the first active area and the second active area, respectively. A first ion implantation process is then performed to implant dopants of a first electric type on a surface of portions of the substrate within the second active area, followed by performing a second ion implantation process to implant dopants of a second electric type on a surface of portions of the substrate within the first and the second active area. Finally, the dopants of each electric type are activated to form a first LDD and a second LDD adjacent to the first gate and the second gate, respectively, the first LDD and the second LDD being of different resistance values.
Because the present invention uses two ion implantation processes to let the driver transistors and the access transistors have different dopant concentrations, different resistance values are acquired to increase cell ratio. Moreover, the ion implantation processes according to the present invention can be performed with other PMOS transistors at the same time, so that no additional mask process is needed, which lowers the process cost. Therefore, the present invention avoids drawbacks of incurring additional process costs and increases of SRAM integration according to the prior art.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.